Hardware Design and Evaluation of Cell Allocation Cache

Tomoaki Ikari, Takahiro Sasaki

Abstract


Multi-core processors are widely used to improve performance of computer systems. To achieve both high per- formance and low power consumption, many researches from device level to processor architecture or application software level have been done. This paper focuses to cache system which is one of the significant module consuming large power. To achieve both high performance and low power consumption, Cell Allocation Cache is proposed which is similar to dynamic cache partitioning technique, but it allocates cache spaces called “Cell” which is smaller than a way. Cell Allocation Cache can achieve better performance than normal cache and cache partitioning. The previous research evaluates the performance of the Cell Allocation Cache. However, circuit scale has not been clarified because detailed design is not performed. This paper evaluates circuit scale of Cell Allocation Cache and shows the hardware overhead.


Keywords


Cache partitioning; shared cache; cell allocation cache; high performance and low power; VLSI design

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