An Efficient Implementation of a Support Vector Machine in the FPGA

Yuki Ago, Yasuaki Ito, Koji Nakano

Abstract


The main contribution of this paper is to present an efficient implementation of a Support Vector Machine (SVM) in the FPGA. Our implementation mainly uses the DSP blocks and block RAMs in the Xilinx Virtex-6 family FPGA. Each DSP block is used to compute the product-sum performed for an internal node and the output node of the SVM. The block RAMs are used to store the weights and interim values. They also used to compute the sigmoid function. The experimental result shows that our implementation for a 128 input and 760 output nodes SVM uses 768 DSP48E1 blocks, 800 block RAMs, and 17680 slices in a Xilinx Virtex-6 FPGA XC6VLX240T-FF1156 and runs in 348.554 MHz. Also, it performs the computation for a 128 input and 760 output nodes SVM 2.72×106 times per second.

Keywords


Support Vector Machine; Machine Learning; SVM; FPGA; DSP48 block; Block RAM

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