Implementation of Tree Arbiter for FPGA and Metastability Analysis

Manami Ogino, Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto, Masafumi Kondo


We propose an implementation of an asynchronous arbiter for Field Programmable Gate Array (FPGA) which can reduce failures caused by metastability of RS flip-flop (RSFF). We adopt a binary tree structure of 2-input arbiters, which is called a tree arbiter. The tree arbiter has hierarchical structure of 2-input arbiters, in which each 2-input arbiter selects one of the two requests progressively. The tree arbiter can prevent increase of latency and has also an advantage in throughput. The 2-input arbiter has glitch killer circuits in order to prevent the failures caused by metastability of RSFF. However, it is impossible to implement the glitch killer circuits into FPGA. Therefore, we propose a method for preventing such failures applicable to FPGA. We also analyze the metastability of RSFF implemented with a crossed connection of logic blocks. Finally we generate a circuit model from implemented FPGA in order to take place an analysis by SPICE. 

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