Proposal of Less Trap Architecture with Better Cache Utilization
Hardware and software interrupts negatively affect system performance primarily because of pipeline flushing and pollution of TLB and caches. We propose a new architecture that focuses on the performace degradation caused by hardware and software interrupts. To reduce this performance degradation utilizing TLB, data and instruction caches effectively, our pro- posed architecture includes three proposals: clock interruption reduction with scheduler processor, a syscall thread of FlexSC  on scheduler processor, and non-busy waiting polling by non- blocking system calls on the syscall thread of FlexSC.
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