High-Speed Implementation of Encryption Circuit using a High-Level Synthesis Tool

Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa


It is mainstream to describe the design of a circuit in hardware description languages such as VHDL or Verilog HDL. In contrast, many high-level synthesis tools which provides the way to implement a circuit using a software programming language, such as C language, are released in late years. Therefore, in this paper, we discussed the implementation methods of high-speed encryption circuit using a high-level synthesis tool. Then we implemented two kinds of encryption circuit (MISTY1 and AES) by 4 different types of substitution table on an FPGA using Vivado HLS which is a high-level synthesis tool provided by Xilinx. As a result, the fastest methods of implementation are 1.9 and 37.6 times faster than the slowest methods, in cases of MISTY1 and AES respectively. In addition, the smallest methods of implementation require 10% and 38% smaller circuits area than the biggest methods, in cases of MISTY1 and AES respectively.


High-Level Synthesis; FPGA; SoC; AES; MISTY1

Full Text:



  • There are currently no refbacks.