FPGA implementation of Ciphers using Schematic to Program Translator(SPT)

Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa


With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it is not easy to develop a software program that runs at high speed on accelerators. On the other hand, encryption algorithms are evaluated with not only the strength but also the implementability and the performance. Therefore it is important to compare their performance by throughput using accelerators. We proposed a development tool named SPT(Schematic to Program Translator) for high-speed processing of encryption as well as GPU and FPGA. In this paper, we discussed FPGA implementation of cipher using SPT. In this tool, a C program is automatically generated from figures drawn in accordance with the specifications of the encryption algorithm. These programs are adjusted for the C compiler, CUDA translator and high-level synthesis tool. Moreover, many-core processors, GPU and FPGA can be easily used by passing these programs to the C compiler, CUDA translator and high-level synthesis tool. As a result, circuits generated by high-level synthesis tool(VivadoHLS provided by Xilinx) using C programs generated by SPT can perform encryption process correctly on FPGA, and their performance became faster than manually generated codes.


GUI; Implementation of Encryption Circuit; High-Level Synthesis; FPGA; SoC; AES; Camellia

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