Optimization of Hardware Implementations with High-Level Synthesis of Authenticated Encryption

Makoto Kotegawa, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa


Competition for Authenticated Encryption: Security, Applicability, and Robustness(CAESAR) is carried out as development and an evaluation of new authenticated encryption. We performed hardware implementations with VIVADO High-Level Synthesis which is a tool of Xilinx. This tool is used with some directives for optimization. This paper shows various optimization techniques on the point of speed, area size and the clock frequency.


AES; AES-OTR; Authenticated Encryption; Hardware implementation; High-Level Synthesis; POET; SILC; ZYNQ-7000

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